In this paper, the design and analysis of a 28GHz CMOS Low noise differential amplifier are discussed. A current reuse technique is used to minimize power consumption by stacking two common source amplifiers. The proposed LNA is designed in a 65nm RF CMOS process to achieve an output matched voltage gain of 18.5dB and minimum Noise figure(NF) of 4.6dB. The LNA consumes 10mW from a 1.2 V power supply and exhibits an input-referred 1dB compression point of -16.1dBm. The LNA is designed using transmission lines, inductors, high-Q capacitors and a transformer, and occupies a total area of only 0.13mm^2.