This paper presents a two-phase linear-exponential incremental analog-to-digital converter (IADC) with using second-order noise coupling (NC). In the first phase, it works as a first-order IADC. Then the second-order NC path is activated in the second phase to significantly expedite the accumulation speed. Moreover, during the second phase, the integrator is disabled to achieve a large maximum stable amplitude (MSA). Compared with the prior art with using first-order NC, the proposed architecture could achieve a higher signal-to-quantization-noise ratio (SQNR) while avoiding the noise penalty and keeping the high effectiveness of data weighting averaging (DWA). Mathematical analysis and further simulation results are presented to confirm the theory of the proposed structure.