Minimum operating power limits possible energy sources in IoT nodes. This paper considers dynamic logic circuits based on c-axis aligned crystalline indium-gallium-zinc-oxide FETs as a design style reducing the minimum operating power of digital systems. A method for ensuring timing and signal integrity and the integration into a standard-cell design flow is presented. Based on a generated logic library, a RISC-V CPU with an outstanding estimated minimum operating power of 6.0 pW is presented. This result shows that systems based on this logic family surpass comparable systems based on CMOS technologies in terms of minimum operating power.