Skip to main content
Video s3
    Details
    Presenter(s)
    Jiawei Wang Headshot
    Display Name
    Jiawei Wang
    Affiliation
    Affiliation
    State Key Laboratory of ASIC and System, Fudan University
    Country
    Country
    China
    Author(s)
    Display Name
    Jiawei Wang
    Affiliation
    Affiliation
    State Key Laboratory of ASIC and System, Fudan University
    Display Name
    Jue Wang
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Xu Cheng
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Jun Han
    Affiliation
    Affiliation
    Fudan University
    Display Name
    Xiaoyang Zeng
    Affiliation
    Affiliation
    Fudan University
    Abstract

    This paper presents the first synthesis friendly dynamic amplifier (DA). The proposed fuzzy logic calibration makes its gain robust against process-voltage-temperature (PVT). In addition, the piecewise-linear linearization technique is also proposed for the fuzzy logic to tune the amplification phase, which compensates the time-domain non-linearity of the regeneration voltages, and accelerates the calibration convergence. The proposed DA is designed in 28-nm CMOS process, and verified by post-simulation results. It has a 16 times gain with -3.0%~3.6% deviations against PVT once the calibration converges within 50 cycles.

    Slides
    • A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration (application/pdf)