Details
Presenter(s)
![Jiawei Wang Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/14191.png?h=7544dbce&itok=nhFbZWq-)
Display Name
Jiawei Wang
- Affiliation
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AffiliationState Key Laboratory of ASIC and System, Fudan University
- Country
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CountryChina
Abstract
This paper presents the first synthesis friendly dynamic amplifier (DA). The proposed fuzzy logic calibration makes its gain robust against process-voltage-temperature (PVT). In addition, the piecewise-linear linearization technique is also proposed for the fuzzy logic to tune the amplification phase, which compensates the time-domain non-linearity of the regeneration voltages, and accelerates the calibration convergence. The proposed DA is designed in 28-nm CMOS process, and verified by post-simulation results. It has a 16 times gain with -3.0%~3.6% deviations against PVT once the calibration converges within 50 cycles.