Recent defenses apply hidden state transitions (HST) to a partitioned FSM to protect against oracle-guided and structural attacks. In this paper, a random walk-based security estimation metric is utilized to quantify the security of gate-level masking of the HST triggering topology. A novel coupling capacitance-based HST triggering topology is proposed. An average 8.53x increase in the random walk-based security estimation score and 887x increase in the geometric mean of expected number paths to extract the key is observed for coupling capacitance based HST as compared to traditional topologies. The schematic level equivalent of the proposed technique is implemented on ISCAS\'89 circuits, resulting in an average overhead in area and power of 14.35% and 22.02%, respectively.