In this paper we present an FFT hardware accelerator based on a butterfly (BUT) structure implemented in Rapid Single-Flux-Quantum (RSFQ) superconducting computing. Our design uses a data representation that combines Race Logic (RL) with pulse streams in order to perform arithmetic operations and generate twiddle factors efficiently. Given today\'s stringent area limitations for RSFQ technology, our design aims to maximize area efficiency. Our design shows 2x to 18x higher throughput per area, measured as performance per number of Josephson junctions. Moreover, we demonstrate 20-70% area saving compared to binary RSFQ FFTs.