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Video s3
    Details
    Presenter(s)
    Karthi Srinivasan Headshot
    Display Name
    Karthi Srinivasan
    Affiliation
    Affiliation
    Indian Institute of Technology Madras
    Country
    Author(s)
    Display Name
    Karthi Srinivasan
    Affiliation
    Affiliation
    Indian Institute of Technology Madras
    Display Name
    Glenn Cowan
    Affiliation
    Affiliation
    Concordia University
    Abstract

    In this work, we present a low-power subthreshold implementation of the Izhikevich neuron model, inspired by the circuit introduced by Wijekoon and Dudek. The circuit, designed in the UMC 65nm process, consumes 11.74fJ/spike at a 0.18V supply voltage, while operating on a biological timescale and allowing analog tunability of control voltages so as to exhibit different spiking behaviors. The circuit comprises an integrated digital spike transceiver that communicates with AER arbitration circuitry and generates reset pulses.

    Slides
    • Subthreshold CMOS Implementation of the Izhikevich Neuron Model (application/pdf)