A super-high-resolution capacitance-to-digital converter (CDC) reaching sub-aF capacitance resolution is proposed. The CDC employs continuous-time (CT) low-noise capacitance-to-voltage converters (CVC) followed by a high linearity bandpass ΔΣ ADC (BP-ΔΣM) without any frequency demodulation. Without the demodulation and a narrow-band sensing technique, the proposed CDC achieves sub-aF capacitance resolution while enlarging the input capacitance range with a coarse C-DAC calibration loop. The proposed circuit has been implemented in a 0.35 um CMOS process with 3.3 V power supply voltage. The CDC shows a capacitance resolution of 0.98 aFrms with a capacitance range of 3.1 pF while consuming 4.16 mW.