This work presents a stochastic ring voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) that combines spatial redundancy with staggered averaging to reduce both noise and distortion. Staggered averaging reduces quantization noise more than simple averaging with a single clock phase for the same amount of spatial redundancy for VCO-ADCs. 4 continuous-time (CT) second-order VCO based sub-ADCs are run in parallel, and their outputs are sampled with multi-phase clocks followed by averaging to form the overall ADC output. We present behavioral simulation results and measurement results on the 65nm CMOS test chip. Measurement results show staggered averaging improves SNR by an average of 7.6dB compared to single ADC. In contrast, simple averaging with 4 sub-ADCs can improve SNR by 6dB. The test chip consumes 0.36mW power and has SNDR of 63dB over 0.5MHz bandwidth.