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Presenter(s)
![Henrique Kessler Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/20901.png?h=d02fcbb7&itok=ukFw7FJu)
Display Name
Henrique Kessler
- Affiliation
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AffiliationUniversidade Federal de Pelotas
- Country
Abstract
This paper presents an electrical study on logic functions with up to 4 inputs designed with a standard cell mapping and two automatically generated supergates methodologies. The results indicate that supergate-based designs reduce the average power in 84.4% of the studied cases while reducing area by 12.9%. Despite the supergate design increasing in average the circuit critical delay by 5.8%, it achieves better power-delay-product in 2823 (70.9%) of the 3982 studied logic functions. The reduction of logic levels is the main factor for gains obtained with supergates due to the glitch power reduction.