Presentations
HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Yubin Qin
Improving System Latency of AI Accelerator with On-Chip Pipelined Activation Preprocessing and Multi-Mode Batch Inference
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Zheng Wang
Author(s): Zheng Wang, Wenxuan Chen, Ming Lei, Bo Dong, Zhuo Wang, Yongkui Yang, Chao Chen, Weiyu Guo, Chen Liang, Qian Zhang, Zhibin Yu
Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Prachi Kashikar
FPGA-Accelerated Agent-Based Simulation for COVID-19
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Wayne Luk
Design Optimization for ADMM-Based SVM Training Processor for Edge Computing
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Yi-Yen Hsieh
A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Chi-Wen Weng
Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Chih-Tsun Huang
Author(s): Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-Yu Chen, Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu
An Energy-Efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning
Presented Date:Jul 04, 10:18pm UTCPresenter(s): Aidin Shiri
Chairs
Chair(s)
Display Name
Wei Zhang
- Affiliation
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AffiliationHong Kong University of Science and Technology
- Country
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CountryHong Kong SAR China
Display Name
Kea-Tiong Tang
- Affiliation
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AffiliationNational Tsing Hua University
- Country