This paper proposes an efficient framework for performance evaluation of STT-MRAM at computer architecture-level implemented by GEM5+NVMain in consideration of the reliability issues. The results show that with consideration of reliability issues, the overall average latency and energy of STT-MRAM can be up to 5.996% and 20.65% larger than that of the nominal cases in a computer system-level memory architecture. Because reliability issues are considered during the design phase, our framework can provide more accurate performance evaluation and contribute to a higher yield of STT-MRAM based computer systems.