The automatic sizing of radio-frequency (RF) integrated circuit (IC) blocks in deep nanometer technologies has moved towards process, voltage, and temperature (PVT)-inclusive optimizations, to ensure their robustness. Each sizing solution is exhaustively simulated in a set of PVT corners, thus pushing modern workstations’ capabilities to their limits. This paper presents innovative research towards the automation of RF IC design by using deep learning to assist the simulation-based sizing tools in time-consuming PVT-inclusive optimizations. The proposed PVT regressor inputs the circuit’s sizing and the nominal performances to estimate the PVT corner performances via multiple parallel artificial neural networks. Two control phases prevent the optimization process from being misled by inaccurate performance estimates. The proposed controlled PVT estimator is tested on a state-of-the-art class C/D voltage-controlled oscillator, reducing the workload of the circuit simulator up to 79% while achieving a speed-up factor of 2.92×, ultimately saving more than 16 days of computational effort.