Skip to main content
Video s3
    Details
    Presenter(s)
    Anh-Tien Le Headshot
    Display Name
    Anh-Tien Le
    Affiliation
    Affiliation
    University of Electro-Communication
    Country
    Author(s)
    Display Name
    Anh-Tien Le
    Affiliation
    Affiliation
    University of Electro-Communication
    Display Name
    Trong-Thuc Hoang
    Affiliation
    Affiliation
    University of Electro-Communications
    Display Name
    Ba-Anh Dao
    Affiliation
    Affiliation
    University of Electro-Communications
    Display Name
    Akira Tsukamoto
    Affiliation
    Affiliation
    National Institute of Advanced Industrial Science and Technology
    Display Name
    Kuniyasu Suzaki
    Affiliation
    Affiliation
    National Institute of Advanced Industrial Science and Technology
    Display Name
    Cong-Kha Pham
    Affiliation
    Affiliation
    University of Electro-Communications
    Abstract

    The goal of this research is to solve the cache side-channel attack problem on the open-source RISC-V architecture. Previously, software mitigation techniques and hardware modifications were investigated to address these issues. However, they are either difficult to implement or have resulted in significant performance loss. In this paper, we present a real-time detection method for cache side-channel attacks such as Spectre. We monitor the processor\'s cache behavior with Hardware Performance Counters and analyzing the collected data with a neural network. Because cache side-channels frequently result in a significantly altered cache usage pattern, our neural network is capable of detecting a Spectre attack in our test environment with an accuracy of more than 99%. In our understanding, this is the first time a run-time Spectre attack on the RISC-V architecture has been detected using hardware events and machine learning.

    Slides
    • Spectre Attack Detection with Neutral Network on RISC-V Processor (application/pdf)