Presentations
Optimization of Analog Accelerators for Deep Neural Networks Inference
Presented Date:Jul 08, 01:39pm UTCPresenter(s): Andrea Fasoli
Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing
Presented Date:Jul 08, 01:39pm UTCPresenter(s): Garrett S. Rose
A Process-Variation Robust RRAM-Compatible CMOS Neuron for Neuromorphic System-on-a-Chip
Presented Date:Jul 08, 01:39pm UTCPresenter(s): Vishal Saxena
Author(s): Vishal Saxena
RSSI Amplifier Design for a Feature Extraction Technique to Detect Seizures with Analog Computing
Presented Date:Jul 08, 01:39pm UTCPresenter(s): Yuqing Zhang
Circuit Cost Reduction for Online STDP Using NIPIN Selector as Timekeeping Device in RRAM Synapse
Presented Date:Jul 08, 01:39pm UTCPresenter(s): Ashwin Sanjay Lele
Chairs
Chair(s)
![Vishal Saxena Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/2539001.jpg?h=589afc61&itok=m6Hr6VkT)
Display Name
Vishal Saxena
- Affiliation
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AffiliationUniversity of Delaware
- Country
![Aatmesh Shrivastava Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/AS.jpg?h=201e2d68&itok=qLFykoXl)
Display Name
Aatmesh Shrivastava
- Affiliation
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AffiliationNortheastern University, Boston, MA
- Country