A 32-bit soft processor based on the RISC-V instruction is proposed in this paper. Hierarchical decoding is presented to reduce the redundancy in the decoding stage, which can reduce resource consumption. A performance optimization scheme is also presented in the execution unit, focusing on the operating frequency and instructions per cycle (IPC). The operating frequency is improved by shortening the critical path while IPC is improved by reducing the stall cycles. To show the validity of the proposed processor, it is implemented on a Xilinx Zedboard and compared with a commercial soft processor, i.e., the MicroBlaze processor. The comparison results show that the performance of the proposed processor is 3.75 times higher than that of MicroBlaze with area increasing only 7%.