The utilization of System on Chips (SoCs) for short-living consumer applications has become very popular. To this end, guaranteeing that the SoC is realized on a minimal die area remains a challenge. Current state-of-the-art solutions for this macro placement-problem tackle this problem based on meta-heuristic- and genetic algorithms. However, although such methods are commonly used for macro-placement, they can not guarantee that the macro placement is optimal. In this work, we are proposing the utilization of modern satisfiability solvers in order to generate optimized macro placements. We demonstrate the approach in experiments and made the resulting tool available as open-source.