This investigation proposed an SRAM utilizing an ultra-low power cell, implemented using the 16-nm FinFET CMOS technology. Voltage supply selection of the static RAM cells is done by gating the wordline (WL) enable. There are two operation modes of the SRAM, i.e., the normal and standby mode. In standby mode, the cell wordline is not activated, where the cell operates on a lower voltage level so that the stored bit status is retained. This, in turn, lowers the power consumption of the cell in standby mode. On the other hand, the normal mode is activated when the wordline of the cell is enabled. In this mode, the cells are using the normal voltage supply of the system. Theoretical derivations and an all-PVT-corner post-layout simulations were provided for verification of the functionality and performance. An SRAM of 1-kb capacity is designed based on the propose cell. It is also featured a power delay product reduction circuit. The simulations show an energy per access of 11.8 fJ, which is the lowest to date.