This paper investigates the behavior of the delay of speculative and conventional parallel-prefix adder architectures under variations. The performance of a range of speculative adder variants is investigated comparatively with conventional non-speculative architectures. In order to capture variations generated from a range of process-dependent sources, the analysis considers threshold voltage variations. We employ Spice-level simulations to capture the impact of variations on delay characteristics of the employed CMOS devices. Under nominal voltage and in the presence of threshold variations, speculative architectures are found to still offer a smaller worst-case delay ,i.e., μ+ 3σ, than their conventional counterparts, as well as in a low operating voltage scenario, where the supply voltage is reduced at 0.8V. However, focusing on normalized delay variation, it is here found that speculative adders are more susceptible to variations, showing a wider delay spread than conventional parallel-prefix architectures around their respective mean values.