This paper compares three different FinFET full-adder topologies based on elementary logic gates regarding the delay and power aspects, considering a traditional design and a design under process, voltage, and temperature (PVT) variations. The delay suffers a deviation of at least 36%, 58%, and 58.5% with PVT variations. The impact on power is around 62.4% for all types of variability. As PVT variability is a crucial concern in nanotechnologies, we also evaluated a mitigation approach based on the addition of sleep transistors. We can obtain circuits up to 39.6% more reliable to the PVT influence with this strategy.