This paper presents an innovative approach toward the automation of the placement task of analog integrated circuit layout design by using an artificial neural network that generates multiple valid floorplan solutions at push-button speed. The proposed model extends the knowledge mining of the most recent layout generation techniques as an end-to-end approach. A novel loss function is used in a semi-supervised fashion for the model to learn how to generate effective placements that follow topological constraints instead of simply trying to copy devices’ locations from some pre-existing labeled dataset of placement solutions. Thus, in addition to eliminating the need for a large dataset of placed sizing solutions for training, the model generalizes better and outputs better layouts for solutions outside the training set. Moreover, one step further is taken towards a model that can predict the placement of different circuit topologies by supporting different encodings (with different number of devices) on the input layer of the artificial neural networks, ultimately fostering an opportunity to reuse incomplete legacy layout information.