This paper presents a second-order VCO-based ΔΣ ADC with a fully digital feedback adder, which is highly digital, area efficient and low power. Both the first and second loop integrator are implemented by VCOs and are free of OTA. A novel digital adder is proposed to realize the secondary feedback, significantly reducing the power and are of the second stage. The proposed ADC is designed in a 28nm CMOS technology under 0.9V supply, consuming only 1.14mW. The simulated SNDR and SFDR are 72.5dB and 84.1dB respectively over a 5MHz signal bandwidth.