As the hardware security gets more and more attentions, Physically Unclonable Function (PUF) has been proposed to provide chip authentication and Intellectual Property (IP) protection effectively. The conventional PUF requires many response clock cycles and independent PUF components, resulting in increased power consumption and area overhead. Recently, STT-mCell has emerged as a promising spintronic device to be used in logic circuit design with significant area and power benefits. However, it is challenging to guarantee the hardware security of this kind of STT-mCell based circuit. In this work, we propose a novel STT-mCell Delay based PUF design (SD-PUF) and exploit the unique manufacturing process variation (PV) on STT-mCell write latency. We introduce a new methodology to select appropriate logic gates in the all-spin chip to generate a unique identification key. Finally, a masking scheme is applied for signature improvement. The experimental results show that the uniqueness of the improved signature is 49.61% and the SD-PUF has significant area benefits over other designs.