Details
Presenter(s)
![Bojun Hu Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/13151_0.jpg?h=9ea14e7a&itok=4R7ldC_f)
Display Name
Bojun Hu
- Affiliation
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AffiliationUniversity of Electronic Science and Technology of China
- Country
Abstract
This paper presents a sampling speed-enhancement technique for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove this technique. The post-layout simulated SAR ADC consumes only6.71_W and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fJ/convertion-step. Simulation results show the proposed speed-enhancement technique improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.