In general, intelligent systems require knowledge databases storing memory associations for mimicking the capabilities of the human brain. Conventional associative memory cells are constructed based on SRAM, a type of volatile memory consisting of large numbers of transistors per stored bit. Here, we present an energy efficient, robust and hardware friendly-associative memory cell design that we designate RC-XNOR-Z. It is based on creating a tuneable RC constant with the help of a modifiable resistance element (RRAM), plus a simplified XNOR gate for generating the output. The overall design has a total component count of 6T1C1R (6 transistors, 1 capacitor, 1 RRAM device), is non-volatile, is designed to work with RRAM devices with very low ON/OFF ratio (approx. 4), avoids high current DC paths during misses and operates under power supply of 0.95V. Furthermore, we show expected simulated power dissipation per miss including refresh in the order of single-digit nW/bit and power dissipation/hit in the order of 10 uW, which for a clock rate of 1GHz translates into aJ and 100s of pJ dissipation accordingly. This is competitive with state of art DRAM and SRAM.