In this paper, we propose a novel high-low interactive memory access pattern for the configurable out-of-place NTT design. Moreover, we present the first quantitative analysis of the correlation between the degree of parallelism and the number of computing cycles, and put forward a conflict-free and universal method of reducing the computing cycles in configurable NTT designs. Based on the above optimization techniques, we develop the first configurable out-of-place NTT architecture that can achieve high area efficiency.