We present a reliability improved read circuit and a feedback-assisted self-termination write circuit, achieving high-density and low power MRAM arrays with high tolerance to process and temperature variation for future integrated cache operation. Based on 16 nm FinFET technology and post-layout simulations, the read circuit achieves 92.09 fJ/bit read energy considering 4.5 sigma variations and the worst case high-to-low resistance ratio. Our write circuit generates a self-terminating control signal by comparing and latching. It detects the exact time required for each writing and saves an 82.3% of write power by eliminating redundant write time from low WER requirements.