A switched-capacitor (SC) step-down DC-DC converter reconfiguring its open-loop topology based on the input voltage to resolve the efficiency issue of single topology is presented in this paper. An adaptive switch modulation (ASM) technique, modulating switch width of the power stage, and a frequency scaling (FS) technique, scaling the sampling rate of the PFM controller, are also proposed to reduce quiescent current of the converter for light-load efficnecy. The prototype converter in 0.25-μm CMOS process with integrated flying capacitors generates a fixed regulated output voltage of 1.8V from an input voltage ranging from 3V to 4.2V. Experimental results show that the gate driving loss and the PFM controller power are decreased by more than 70% with the ASM and FS techniques. The light-load efficiencies are enhanced with 7% and 10% when the input voltage is 3V and 4V, respectively. The transient response time is about 500ns after a step load current from 50μA to 10mA. Its power efficiency is high than 70% over a wide load current range with a peak value of 83%.