In this article, we propose a multifunction computing unit for training deep neural networks by reusing computing resources based on a piecewise linear (PWL) method. Based on the state-of-the-art segmentor, multiple nonlinear functions are divided into the fewest segments with the same bit width of computation. In hardware implementation, the reconfigurable technique is implemented on multiple functions while reusing computing resources including the multiplier and adder. The application-specific integrated circuit (ASIC) implementation results reveal that the architecture with reuse reduces the area by 44.50% and the power by 43.71% at the same frequency, when compared with the architecture without reuse.