This work demonstrates how adiabatic switching can be used to reduce the power consumption in N-path-filter based receiver designs. To maintain a good filtering and switching performance while avoiding interferer pulling of the oscillator, an integrated class-F VCO with enriched 3rd order harmonic is used, operating at 2x RF input frequency for divider-based IQ generation. A test-chip was fabricated in a 1P6M 180nm CMOS technology confirming a low power consumption of 5.2mW from a 1.2V Supply.