This paper describes a system architecture for a digital pre-distortion (DPD) algorithm that compensates for nonlinearity with memory. For this purpose, a digital model is used to represent the analog front-end power amplifier nonlinear distortion, and frequency selectivity. A DPD algorithm is presented, and the implementation constraints are defined. The digital pre-distorter linearization accuracy is assessed using a signal with a PAPR of 8dB and a fractional bandwidth of 15%. The signal is applied to a realistic power amplifier model in high compression, and with frequency selectivity. Through simulation, it is found that the polynomial equation with memory required to maintain an error below 5% requires a nonlinear order of 8, and a number of memory elements equal to 5.