Details
Presenter(s)
![An-Jung Huang Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/10621_0.jpg?h=8f391919&itok=8zps07rn)
Display Name
An-Jung Huang
- Affiliation
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AffiliationNational Yang Ming Chiao Tung University
- Country
Abstract
Deep learning based super-resolution achieves high-quality results, but its heavy computational workloads, large buffer, and high external memory bandwidth inhibit its usage in mobile devices. To solve the above issues, this paper proposes a real-time hardware accelerator with the tilted layer fusion method that reduces external DRAM bandwidth by 92% and just needs 102KB on-chip memory. The design implemented with a 40nm CMOS process achieves 1920x1080@60fps throughput with 544.3K gate count when running at 600MHz; it has higher throughput and lower area cost than previous designs.