Details
Presenter(s)
Display Name
Wei Wang
- Affiliation
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AffiliationNankai University
- Country
Abstract
This paper presents a binary-weighted resistive load interpolation digital-to-analog converter (RIDAC) architecture with improved resolution performance. The RIDAC consists of coarse resistor string DAC driving a multi-input operational amplifier where the interpolation is performed inside the load branch of this amplifier. The shared resistive load provides an accurate and monotonic binary-weighted interpolation between coarse voltage levels with a reduced number of resistors.