Multipliers are present in a large variety of applications. However, it is usually responsible for most of the power dissipation. On the other hand, squared multiplier is a special case of the general-purpose multiplier which both operands are the same, proportioning many of architecture optimizations. This paper introduces the radix-2textsuperscript{$m$} squared array multiplier architecture. Our architecture proposal for the squared multiplier is the first to reduces the partial products by splitting the operands into $m$-bit groups. Our squared multiplier architecture explores different adder schemes in the multipliers adder tree. As a case study, we demonstrate our squared multiplier proposal for $m$=2 (radix-4), We investigated the Wallace and Dadda addition trees employing as final carry propagating adder (CPA) the Ripple Carry adder (RCA) as well as with the adder automatically selected by the synthesis tool.