Approximate computing, an emerging technique to reduce the area and power consumption of a circuit for error-tolerant ap- plications, is getting rising attention. One key enabling technique for approximate circuit design is approximate logic synthesis (ALS). Many ALS methods are based on a scheme that iteratively selects one single local approximate change (LAC) in each iteration until the error bound is reached. However, this scheme fails to consider the joint effect of multiple LACs whose induced errors may counteract with each other when applied simultaneously. In this paper, we propose a method to select multiple LAC candidates in one single iteration under a given bound on maximum error distance (MaxED). It first builds a miter by adding a multiplexer into the network for each LAC candidate in the network. Then, a quantified satisfiability problem is formulated on the miter and solved to obtain a maximal set of LACs that can be applied simultaneously. The experimental results show that under the normalized MaxED bound of 1% and 5%, our method reduces the circuit area by up to 39% and 70%, respectively.