Neural interfaces allow to better understand the brain by precisely measuring its activity down to single neurons. However, recording a high number of neurons generates a massive amount of data, making wireless transmission difficult. To solve this, we designed a neural recording ASIC comprising a ramp ADC and a spike-by-spike digital compression circuit based on the principal component analysis (PCA). The ASIC comprises 49 channels with an area of 50 x 60 um2 and a power consumption of 4.6 uW. The ASIC measures 1370 x 1370 um2 and consumes 828 uW. This paper presents preliminary performance of the neural recording.