A typical digital low-dropout regulator (DLDO) that is clocked with a fixed frequency suffers from the trade-offs between power, speed, and stability. This paper proposes a DLDO that achieves both fast settling and low power consumption without limit-cycle oscillation (LCO) by adaptively changing the clock frequency and eventually turning off the clock in the steady state. The proposed LDO also features an inverter-based droop-compensation circuit for output-capacitor-free operation. The proposed LDO designed in a 28-nm CMOS process achieves a 70-ns settling time and a 137-mV droop voltage for the 400-mA load current transition with a 2.6-ns edge time, which translates to the figure of merit of 4.8 fs.