Presentations
Mitigation of ''Horn Spurs'' in a MASH-Based Fractional-N CP-PLL
Presented Date:Jul 08, 08:07am UTCPresenter(s): Valerio Mazzaro
A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation
Presented Date:Jul 08, 08:07am UTCPresenter(s): Xinyu Xu
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems
Presented Date:Jul 08, 08:07am UTCPresenter(s): Luigi Grimaldi
A 2.5-5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS
Presented Date:Jul 08, 08:07am UTCPresenter(s): Gautam R
A Novel Charge Pump with Ultra-Low Current Mismatch and Variation for PLL
Presented Date:Jul 08, 08:07am UTCPresenter(s): Shujiang Ji
Chairs
Chair(s)
Display Name
Sohmyung Ha
- Affiliation
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AffiliationNew York University Abu Dhabi
- Country
Display Name
Luis Oliveira
- Affiliation
-
AffiliationUniversidade Nova de Lisboa
- Country