A digital pre-distortion of a sub-THz transceiver with an antenna array is proposed. The best trade-off between complexity and accuracy is obtained by applying closed-loop techniques and orthogonal characteristics. The modules with a sampling rate of 7.04 GHz are successfully implemented with 16nm FinFET CMOS process using an eight parallel architecture. The effect of time variation is considered and a post-training mechanism is provided. Based on IEEE 802.15.3d, incorporating with various non-ideal effects, the error vector magnitude of the whole transmitter can reach -20.64 dB, satisfying the specification criteria.