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Video s3
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    Presenter(s)
    Vipul Bajaj Headshot
    Display Name
    Vipul Bajaj
    Affiliation
    Affiliation
    Indian Institute of Technology Madras
    Country
    Abstract

    This work presents a 12 bit SAR ADC embedded in a first-order noise shaping loop to obtain a 16 bit resolution while maintaining sample-by-sample correspondence. Using a sub-quantization DAC in parallel with the LSB DAC allows the conversion cycles to be shorter than the first, increasing the effective sampling rate. Dynamic element matching is used in the 6 bit MSB DAC. The integrator in the loop filter is implemented with minimal overhead using one of the stages of the multi-stage preamplifier in the comparator.

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