Details
Presenter(s)
![Vipul Bajaj Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/24651.jpg?h=60914f74&itok=5rXOJIiq)
Display Name
Vipul Bajaj
- Affiliation
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AffiliationIndian Institute of Technology Madras
- Country
Abstract
This work presents a 12 bit SAR ADC embedded in a first-order noise shaping loop to obtain a 16 bit resolution while maintaining sample-by-sample correspondence. Using a sub-quantization DAC in parallel with the LSB DAC allows the conversion cycles to be shorter than the first, increasing the effective sampling rate. Dynamic element matching is used in the 6 bit MSB DAC. The integrator in the loop filter is implemented with minimal overhead using one of the stages of the multi-stage preamplifier in the comparator.