A digital multi-range duty cycle correction (DCC) circuit is presented to correct the differential duty cycle distortion in a multi-standard half-rate SerDes transceiver. A novel 9-state inverter is used for enhancing the system granularity and reducing the loading by ~75%. In addition, the system allows two different correction locations and 7 different correction ranges. Each range is optimized to minimize the jitter for specific data rates as well as ensures enough coverage. The DCC loop is implemented in 7 nm FinFET technology. It supports a frequency range of 7 – 14 GHz with a power consumption of 1.25 – 2.35 mA.