This works presents a design methodology to re-optimize legacy Register-Transfer level (RTL) designs specified in synthesizable Verilog or VHDL through High-Level Synthesis (HLS). The proposed methodology is based on an RTL to C compiler that converts synthesizable RTL descriptions into functional equivalent behavioral descriptions optimized to maximize its re-usability though HLS. This implies stripping of all the timing information from the RTL description and generating only C/C++ code that is functionally equivalent that has arrays, loops and functions. Generating these structures is very important in order to maximize the re-optimization potential as commercial HLS tools make extensive use of synthesis directives in the form or pragmas (comments) that allow HLS users to control how to synthesize them. Thus, generating C/C++ code with a larger number of these structures ensures that a larger variety unique implementations with different area vs. performance and power trade-offs can be generated from the converted C/C++ code. Experimental results with a variety of applications from different domains show the effectiveness of your proposed flow.