This work investigates the Mirror full adder circuit at 7nm FinFET technology, considering the SET susceptibility and the robustness of all internal nodes in the circuit. This work aims to identify how this full adder topology behaves in a specific environment, observing the charge collected for each internal node. The devices involved in the processing of the carry-out function shown to be more robust than the Sum circuit and also presented a lower error rate. Furthermore, the input vector 000 proved to be the most critical among the input combinations, and the results show a dependence of the type of pulse in the generation of errors in the Mirror full adder.