This paper proposes a novel metastability inference and avoidance (MIAA) technique, which can significantly mitigate metastability risks by inferring and avoiding potential metastability risks. A 40nm GALS 2x2 NoC design with the proposed MIAA circuit is simulated at 0.4V voltage condition to verify its function and performance. The post-layout simulation results show that the proposed MIAA can effectively reduce the metastability condition rate to zero across a wide range of frequency ratios. MIAA enables a single flip-flop for metastability-free synchronization, thereby improving the latency and throughput of the NoC by 40.2% and 79%, respectively.