In this paper, parasitic resistors and capacitors which are created by via, a passive source of entropy, highly dependent on process variation is introduced to a latch-based PUF. The parasitic capacitors and resistors are implemented by using metal2 to metal7 in 65nm TSMC technology node. Measurement results show without using any post stabilization, 1.29% instability, with 2000 repeated evaluations, is achieved. PUF evaluated over supply voltage and temperature from 0.8 V to 1.3 V and 0 °C to 105 °C, respectively. Instability of worst-case varies from 3.1% to ~1.9% over supply voltage and from ~1.9% to ~2.2% over temperature. 103X distance ratio between inter and intra die hamming-distance is obtained.