This work introduces a new VCO-ADC architecture. The power supply nodes of the inverters in a ring oscillator are sorted in two sets, and connected to two different input signals. We show in this paper that the oscillator frequency of such configuration reacts to the product of the two inputs. Therefore, the ring oscillator can be used both as a mixer and to digitally acquire the lowpass converted component. A first system-level approach is made to optimize the distortion by a proper number of taps in the ring oscillator. To confirm the system level predictions, some circuit simulations have been made. As a result, it is observed that VCO non-linearity limits the SNDR in a similar way as in conventional low pass VCO-ADCs. In a 65nm CMOS process, 55dB of SNDR is achieved in a 5-MHz bandwidth for a 1MHz downconverted signal, using a sampling clock of 2.5 GHz and input signals centered in 70 MHz and 71 MHz.