Current monolithic quantum computer architectures have limited scalability. One promising approach for scaling them up is to use multi-core architectures, in which different quantum processors are connected via quantum and classical links. This new architectural design poses new challenges such as costly inter-core communications. To reduce these movements when executing a quantum algorithm, an efficient mapping technique is required. In this paper, a detailed discussion of the quantum circuit mapping problem for multi-core quantum architectures is provided. We furthermore explore the performance of a mapping method, formulated as a partitioning over time graph problem, by performing an architectural scalability analysis.