This paper proposes a logarithm posit processing element (LPE) for the DNN training processor. By exploiting the 8- bit posit format to store operands, it reduces 58.2% memory access for both off-chip DRAM and on-chip SRAM. Meanwhile, to reduce the massive power consumption from the complicated float-point computation and accelerate training, we transform the calculation into the logarithmic domain, which is simple to achieve. It saves 49.24% training energy and offers a 1.68× speedup. Moreover, we adopt a two-stage accumulation unit to achieve high accumulation precision with a low bit-width. With the proposed LPE, our processor reaches 3.87TFLOPS/W, which outperforms the previous work 1.79×. The proposed LPE is feasible for edge-devices training.