A resistor-less hybrid loop filter is introduced as part of a 12.6GHz~14.5GHz low-jitter PLL in TSMC 3nm FinFET technology. The hybrid loop filter eliminates the large integration capacitor and resistor by leveraging a digitized integral path (IPATH) and a differential sample-and-hold (S/H) proportional path (PPATH). While saving much area and gaining flexible loop adjustments, the scheme significantly improves the control voltage ripple, as well as in-band noise. The PLL achieves 55fs-rms (1kHz to 100MHz) and 71fs-rms (full band) random jitter with a loop bandwidth of ~3MHz, dissipating 18.6mW from 0.875V supply. The simulated reference spur can be suppressed to be <-98dBc using a comparator input offset of ~5mV.