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Video s3
    Details
    Presenter(s)
    Saito Shibata Headshot
    Display Name
    Saito Shibata
    Affiliation
    Affiliation
    The University of Tokyo
    Country
    Author(s)
    Display Name
    Saito Shibata
    Affiliation
    Affiliation
    The University of Tokyo
    Display Name
    Yoshiki Sawabe
    Affiliation
    Affiliation
    The University of Tokyo
    Display Name
    Kota Shiba
    Affiliation
    Affiliation
    The University of Tokyo
    Display Name
    Atsutake Kosuge
    Affiliation
    Affiliation
    University of Tokyo
    Display Name
    Mototsugu Hamada
    Affiliation
    Affiliation
    University of Tokyo
    Display Name
    Tadahiro Kuroda
    Affiliation
    Affiliation
    University of Tokyo
    Abstract

    A pad-less 5GHz RFID employing complementary pass-transistor adiabatic logic is proposed. The power clock that drives the whole CPAL is improved to enable a smaller input RF power and higher speed data frequency by using a power clock shaper which pulls the power clock to GND when a falling edge is detected. Additionally, a new CPAL circuit exploiting both the threshold voltage and W/L of the transistors is proposed. Measurements confirm that the proposed RFID can communicate at a distance of 11cm with 12dBm transmission power, as well as at a 100kbps data rate across a distance of 1cm.

    Slides
    • A Low-Power RFID with 100kbps Data Rate Employing High-Speed Power Clock Generator for Complementary Pass-Transistor Adiabatic Logic (application/pdf)